Sequence Design, EDA’s power-aware SoC design technology leader, has released new versions of CoolTime and CoolCheck for complete power-grid verification of the most advanced SoC designs, with improved usability, analysis, and optimization features to minimize set-up times and maximize user productivity. These usability improvements have dramatically improved the time it takes to achieve design closure by making it much easier to understand and debug results, particularly in IOs where nets are virtual, existing in GDS, but not in LEF.
CoolCheck provides unique formal grid verification, while CoolTime solves for timing and signal integrity, static IR drop, electromigration (EM) and dynamic voltage drop. With more than 150 successful tape-outs at customers worldwide, CoolTime addresses problems unique to nanometer SoCs using 130, 90, and 65nm processes with a concurrent engine that accelerates design closure for even the largest, high-performance designs.
CoolCheck is the only formal power-grid verification tool capable of detecting errors that both static and dynamic voltage-drop fail to find:
- With increasing numbers of components to be powered up, CoolCheck enhances designer productivity by providing 100% detection of structural defects (missing vias, etc.) and connectivity defects (high resistance, etc.) in the grid as early as the floorplanning stage of the design flow
- Significant enhancements to the user interface, including new visual reports and automated navigation, enable designers to effectively and quickly probe results
- Provides results for large chips in less than a day (on a 2 million instance chip, extraction of the power grids took 5 hours, and the analysis engine 2 hours, running on a 32GB, 64bit processor)
Eliminating the need for multiple point tools and iterations, CoolTime is the only nanometer SoC design tool that takes dynamic voltage drop into account while computing timing and signal integrity in a single tool. Sequence¡¯s award-winning Columbus extraction technology allows accurate power-grid parasitic extraction supporting advanced copper modeling and metal-fill effects.
The latest CoolTime release features improved usability and accuracy features:
- Tool setup time is minimized with automation of power-grid parasitic extraction and enhanced handling of pad ring (e.g., reconciles differences in power net names in IOs, if GDS and LEF names are inconsistent)
- Reporting is enhanced with metrics that provide the designer with a complete understanding of the power grid for multiple rails
- The user interface comes with significant improvements to navigation and messaging that make the tool intuitive
- CoolTime’s handling of complex clocking schemes is improved to reduce occurrences of undetected faults
- Improved modeling and accuracy of voltage-aware timing analysis limits layout changes and iterations to only the ones necessary, while mitigating risk of voltage-induced functional failures
- Competing solutions that rely on multiple point tools can generate unreasonably high numbers of layout changes across multiple iterations by using worst or average voltages
- Speeds design time by providing vectorless dynamic voltage drop analysis for complex chips. For example, hierarchical designs with 10-15M instances have run in less than 3 hours with full timing and signal integrity analysis, an improvement of 8X over previous versions. The same 10-15M instance designs, run flat, now have run in 14-15 hours, an improvement of 2X.
“As the level of design complexity grows, it is essential that we provide designers with tools that are both accurate and efficient,” said Vic Kulkarni, Sequence president and CEO. “These new releases of CoolTime and CoolCheck ensure fast working silicon, combining superior analysis with a user-friendly interface.”
Upgraded versions of both tools are available now. CoolTime pricing for a 1-yr time-based license in North America begins at $70,000, and pricing for the CoolCheck option to CoolTime begins at $40,000. For mofe information send email or go online.