Lattice Rolls Out ispLEVER 6.0 Programmable Logic Design Tool Suite

Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of its ispLEVER(R) 6.0 programmable logic design tool suite. Fully supporting the newest 90nm LatticeECP2TM High-Performance, Low Cost and LatticeSCTM Extreme PerformanceTM System Chip FPGA families, ispLEVER 6.0 boasts unprecedented performance and significant design flow enhancements. Key highlights of the ispLEVER 6.0 release include support for the industry’s fastest 90nm FPGAs, the introduction of a new, highly integrated Design Planner interface, improved support for schematic FPGA design and an expanded library of IPexpressTM user-configurable IP cores.

“Our ispLEVER design tool suite now delivers industry leading timing closure capability to FPGA designers,” said Chris Fanning, corporate vice president of software and IP solutions. “Our LatticeECP2 and LatticeSC FPGA families achieve unprecedented performance levels in ispLEVER 6.0. This exceptional performance, coupled with our more efficient Design Planner interface, enables our customers to lower their design cost and accelerate time-to-market.”

“We are winning significant new FPGA designs, and our ispLEVER design tools are one compelling reason why,” said Stan Kopec, corporate vice president of marketing. “FPGA designers derive significant value from our tools’ robust feature set, superior performance, and the ease of use that our tools, design flows and documentation provide,” Kopec concluded.

New Design Planner Integrates Preference Editor and Floorplanner
Lattice’s new Design Planner integrates the two most used optimization tools, Preference Editor and Floorplanner, to more closely mirror the thought process and work flow of expert FPGA designers. Now users can move seamlessly from one task to another without unnecessary intermediate steps. The Preference Editor is used to define design parameters such as critical paths and timing objectives, which, because they are by definition device-specific, cannot be specified at the Hardware Description Language (HDL) level. The Floorplanner supports detailed control of logic placement within a device. Integrating these two interrelated tools greatly simplifies tasks such as assigning customized logic to physical device I/O pins. With this new approach, designers have a unified tool that helps them work seamlessly to complete these design tasks more quickly and efficiently.

IPexpress Expansion
The new IPexpress flow will significantly reduce design time by allowing IP parameterization and timing analysis on the designer’s desktop. By configuring IP cores using the IPexpress flow, designers are able to simulate, place and route, generate netlists and run static timing analysis with their own logic and selected core parameters in real-time. In addition, a new hardware evaluation capability minimizes design risk by allowing free trial use of the cores prior to the purchase of an IP core license. IPexpress-supported functions include DDR, Ethernet, FIR, FFT, PCI and Reed-Solomon encoder and decoder. Lattice intends to make several more IPexpress cores available throughout the year.

Industry Leading Synthesis and Simulation
Lattice continues to work closely with third party synthesis and simulation partners Mentor Graphics(R) and Synplicity(R) to provide designers with industry-leading solutions as a standard ispLEVER feature. All third-party tools have been updated with performance enhancements for Lattice FPGAs. Included in the ispLEVER design suite are Mentor Graphics’ Precision RTL(R) synthesis version 2005c and ModelSim(R) simulator version 6.1d, and Synplicity’s Synplify(R) synthesis version 8.5d.

“Lattice Semiconductor’s new FPGAs and ispLEVER design tool suite, combined with Mentor Graphics’ Precision(R) award-winning analysis capabilities, gives users the tools to quickly reach their design goals,” said Simon Bloch, general manager of Mentor Graphics’ Design Creation and Synthesis Division. “Our close partnership with Lattice Semiconductor allows us to fine tune the Precision RTL synthesis engine to deliver maximum quality of results for Lattice customers.”

“We believe that the extreme performance and low cost delivered by the LatticeSC and LatticeECP2 FPGAs together with the QoR, runtime, and ease-of-use benefits of our market-leading Synplify and Synplify Pro synthesis tools will provide Lattice customers with a significant advantage,” said Andy Haines, Synplicity’s Vice President of Marketing. “With the advanced architecture and features of these devices, Lattice has emerged as an innovative force in the FPGA market.”

New Schematic Design Library for Lattice FPGAs
The most efficient way for many designers to visualize and implement designs is through a schematic interface. In ispLEVER 6.0, a new schematic design library for the ispLEVER Schematic Editor allows designers to develop gate-level circuits based on library elements from the ispLEVER FPGA Libraries Help System. The libraries contain standard Boolean gates, latches, flip-flops and I/O buffers compatible across all Lattice FPGA device families. A new tutorial included in ispLEVER 6.0 provides design examples using a mixture of gate-level schematics modules generated by IPexpress, and RTL blocks to complete a design with the Schematic Editor. The new Lattice FPGA schematic library supports the LatticeECP2, LatticeECPTM/LatticeECTM, LatticeSC, LatticeXPTM and MachXOTM families.

Other Improvements to ispLEVER Design Tools Include:

  • Design preferences can be viewed during place and route operation
  • Updated HTML reporting structure, format and information
  • New ispLeverDSP Block sets for use with MATLAB/Simulink design tools
  • Updated simulation libraries for use with Aldec Riviera and Active-HDL tools
  • Enhancements to the ispLEVER text editor
  • New manuals and tutorials that cover DSP design, IPexpress flow and FPGA schematic design

A complete list of these and other new features and enhancements to the ispLEVER 6.0 design tool suite can be viewed at online.

Pricing and Availability
The ispLEVER 6.0 software for Windows, supporting all Lattice digital programmable logic families, is priced at an industry best value of $695 and is available immediately. UNIX and Linux versions also are available.

About Lattice Semiconductor
Lattice Semiconductor Corporation provides the industry’s broadest range of Field Programmable Gate Arrays (FPGA) and Programmable Logic Devices (PLD), including Field Programmable System Chips (FPSC), Complex Programmable Logic Devices (CPLD), Programmable Mixed-Signal Products (ispPAC(R)) and Programmable Digital Interconnect Devices (ispGDX(R)). Lattice also offers industry leading SERDES products. Lattice is “Bringing the Best Together” with comprehensive solutions for system design, including an unequaled portfolio of non-volatile programmable devices that deliver instant-on operation, security and “single chip solution” space savings. Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, industrial, consumer, automotive, medical and military end markets. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124-6421, USA; telephone 503-268-8000, fax 503-268-8037.

Lattice Semiconductor Corporation, Lattice (& design), L (& design), Extreme Performance, IPexpress, LatticeECP2, LatticeECP, LatticeEC, LatticeXP, MachXO, LatticeSC, ispLEVER and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.