Zarlink Verifies Ultra Low-Power SoCs with Cadence Virtuoso Platform

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Zarlink Semiconductor (NYSE/TSX:ZL) has used its Cadence(R) Virtuoso(R) custom design platform to successfully verify its ultra low-power communications chips. Zarlink, a leading provider of solutions for the medical field, chose the Virtuoso Specification-driven Environment, along with Virtuoso NeoCircuit, to further improve the productivity of its mixed-signal and RF designers. With the Virtuoso platform’s enhanced design verification, Zarlink made significant improvements in time to market and anticipates further gains as these technologies are deployed throughout the company.

Zarlink provides complex mixed-signal system-on-chips (SoCs) with state-of-the-art performance, often for medical applications involving implanted or BAN/PAN equipment. These SoCs must work from a small battery supply for many years, drawing no more than micro-amps averaged over their lifetime. The pressure to get to market quickly adds to the high demand for thorough design methodologies with faster verification over process corners, supply and temperature.

“Traditionally, verification over process and environmental variations have been carried out using exhaustive OCEAN scripting,” said Arshad Madni, principal RF IC design engineer at Zarlink. “With the Virtuoso Specification-driven Environment, our ultra low-power designers now spend significantly less time in script development and more time on analyzing the simulation results.”

“We found that Virtuoso NeoCircuit further enhances the throughput of our designers,” added Dr. Steve Morris, director of R & D at Zarlink. “This product allows our design teams to utilize the optimizer feature to expedite the time-consuming analysis needed to achieve well-toleranced circuit performance, leaving designers with time to work on more creative engineering tasks.”

Virtuoso Specification-driven Environment and Virtuoso NeoCircuit are advanced design and simulation environments for the Virtuoso platform. By supporting extensive exploration of multiple designs and auto-sizing them to their objective specifications, all with distributed simulation management, Zarlink is now able to develop high-quality, well-tested designs in a shorter period of time.

“An important element in all custom designs is the thorough analysis needed prior to releasing a circuit to manufacturing, ensuring all specifications are met over process and environmental constraints,” said Charlie Giorgetti, corporate vice president, Product Marketing, at Cadence. “The advanced design environments available within the Virtuoso platform set the standard for fast and accurate circuit exploration and validation.”

The Virtuoso platform is a comprehensive system that helps enable design teams to deliver silicon that meets specifications, as well as schedules. It includes a specification-driven environment, multi-mode simulation, accelerated layout, advanced silicon analysis, and a full-chip integration environment.

For more information on Zarlink’s solutions, go online.

About Cadence
Cadence enables global electronic-design innovation and plays an essential role in the creation of today’s integrated circuits and electronics systems. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed-circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centres, and research facilities around the world to serve the global electronics industry.