Sequence and Arithmatica to Advance SoC Low-Power Design

Sequence Design announces that Arithmatica, Inc. has joined its In-Sequence Technology Partner Program, permitting the two companies to significantly advance SoC low-power design technologies and methods. The In-Sequence Program promotes technology advances for power-aware design flows, modeling accuracy, EDA interoperability and research through the alignment of technology partners and academia.

Arithmatica has introduced version 3.0 of the CellMath datapath design tools, incorporating power-knowledgeable synthesis and an extended Verilog interface capable of specifying robust datapath structures. CellMath version 3.0 users typically reduce power by an additional 10 percent to 20 percent over current results in their complex datapath circuits.

Sequence’s PowerTheater is the industry standard for low-power design at RTL where 80 percent of a chip’s power budget is set. Capabilities range from early RTL analysis to full-chip power estimation and physically-aware power reduction for today’s largest designs. PowerTheater allows users to begin the design process with a firm handle on power budgets – before synthesis, when it is too late for significant power reduction – and perform full chip RTL Power Signoff with verified results that correlate to silicon. Arithmatica is working closely with Sequence on RTL modeling, and at the gate level to “power-certify” their datapath results.

Arithmatica is the latest in a series of In-Sequence partnerships, joining a variety of EDA vendors, foundries, IP providers, design services, platform vendors and universities.

For details on In-Sequence, contact the company at, or go online.